This invention relates generally to the testing of integrated circuits, and more particularly to an apparatus and method for testing sets of integrated circuits simultaneously with two or more testers.
Semiconductors are widely used to manufacture integrated circuits for electronic applications, including computers, radios, televisions, digital cameras, and personal computing devices, as examples. Such integrated circuits typically include multiple transistors fabricated in single crystal silicon. For example, there may be millions of semiconductor devices manufactured on a single semiconductor product. With the trend towards downsizing electronic devices, there is a need to manufacture smaller integrated circuits and package the integrated circuits in smaller packages. The manufacturing and testing of downsized integrated circuits and packages presents many challenges.
Integrated circuits are typically manufactured by depositing a plurality of conductive, insulative, and/or semiconductive material layers on a semiconductor substrate, and patterning the various material layers using lithography processes to form devices and interconnects that perform the electrical functions of the integrated circuit. Usually, hundreds or thousands of integrated circuits are manufactured on a single semiconductor wafer. The wafer is then tested, by a wafer probe test, for example, which tests single integrated circuits (IC""s) on the wafer at a time, or groups of single IC""s at a time.
The integrated circuits that pass the wafer probe test are packaged after singulation. Packaging is typically required because the integrated circuits are too small to be electrically coupled directly to printed circuit boards. Although usually, a single integrated circuit is packaged in a single package, alternatively, a plurality of integrated circuits may be packaged in a single package, known as a hybrid IC.
Typically, an integrated circuit is packaged by attaching the device to a substrate or some other material more rigid than the integrated circuit wafer material, often with the package being larger than the integrated circuit. The IC package usually comprises a plurality of contact terminals that may be used to couple the packaged integrated circuit to a printed circuit board or other device, depending on the application.
An example of a prior art IC test apparatus 100 is shown in FIG. 1. Test apparatus 100 comprises a xe2x80x9chigh costxe2x80x9d test apparatus, referred to as xe2x80x9chigh costxe2x80x9d because of the high expense of the tester 108, and therefore, the high expense per IC of running tests on IC""s. The high cost test apparatus 100 may cost hundreds of thousands to millions of dollars (U.S. $), for example, and may be used to test packaged IC""s.
The high cost test apparatus 100 includes an input station 102 coupled to a handler 104, with an output station 106 coupled to the handler 104 on the opposite side. The test apparatus 100 includes a tester 108 which is typically a high cost piece of equipment that includes control circuitry and test electronics, and includes storage for storing the IC test information obtained. The test apparatus 100 includes a monitor 138 and console 142 adapted to receive instructions from and provide information and communicate test results to an operator. The monitor 138 and console 142 may be integral to the tester 108 or handler 104, for example (not shown).
The test apparatus 100 includes a test head 110 that is coupled to the tester 108 by a cable or wiring 112. The test head 110 is coupled to and interfaces with the handler 104 using load board 114. The load board 114 is adapted to support packaged integrated circuits under test, and may comprise one or more sockets 116 adapted to support the integrated circuits or devices under test. The handler 104 may include an environmental chamber (not shown) for high and/or low temperature tests, and the handler 104 may also include robotic equipment such as pick and place machines and conveyor belts that are adapted to move IC""s from the input station 102 through the handler 104, to the load board sockets 116, to the output station 106.
The input station 102 may include a plurality of input IC trays 118, with each input IC tray 118 being adapted to hold and support a plurality of IC""s to be tested. An operator of the test apparatus 100 loads the input IC trays 118 with the IC""s, for example, in an array of rows and columns. The input station 102 may include a pneumatic vacuum plunger 122 that is adapted to remove IC""s from the input IC tray 118 and place them in the interim tray 124, for example. The input station includes a robotic pick and place mechanism 120 that is adapted to facilitate the movement of the IC""s from the input IC tray 118 using the plunger 122.
IC""s are transferred using the interim tray 124 into the handler 104 through the input port 126. Inside the handler, the IC""s are placed using robotic machinery in the sockets 116 on the load board 114. After the IC""s are tested, the robotic equipment moves the IC""s back to the interim tray 124 or to another tray located near the output station 106, and the IC""s are moved to the output station through the output port 128.
The tested IC""s are placed using robotic pick and place mechanism 132 and plunger 134 into output IC trays 130.
The test apparatus 100 shown is considered a high cost tester because not only is the apparatus 100 expensive, furthermore, a variety of rather complicated and time-consuming tests are performed on each device under test. The test procedures performed by high cost tester 100 may included detailed functional test of the IC""s, and may include AC parameter tests, as examples. For digital signal processors (DSP""s), which are complex IC devices, the IC""s may have a large number of pins (e.g. 100 to over 500 pin), and require extensive testing. Some tests may require that the IC""s be thermally soaked, e.g., brought up to a certain temperature, before certain tests are performed on the IC""s. Thermal soaks are time-consuming, and therefore, particularly expensive tests.
Because the high cost test apparatus 108 is very expensive and the time spent testing an IC or set of IC""s is very valuable, often, IC""s are first screened using a low cost test apparatus before being tested on the high cost test apparatus 108. Some tests may be off-loaded to the low cost tester, to save time on the high cost test apparatus 108.
A prior art low cost test apparatus 200 is shown in FIG. 2. The apparatus 200 is referred to as xe2x80x9clow costxe2x80x9d because it is significantly less expensive than a high cost test apparatus 100, e.g., {fraction (1/10)}th of the cost. For example, a low cost test apparatus 200 may cost a few tens of thousands of U.S. dollars.
Low cost test apparatus 200 includes a tester 236 that includes a monitor 238, a control computer 240 which may comprise one or more Sparc station, for example, and a console 242. The tester 236 is coupled by wiring 250 a test head 244. The test head 244 is coupled to a handler 248 via a load board 246. The load board 246 includes a of plurality sockets 252 that are adapted to support and make electrical contact to IC devices under test. An operator of the tester 236 loads the IC devices under test (DUT) into the load board 246, couples the tester to the handler 248, and instructs the tester, using the control computer 240, to perform the low cost tests. Typically, in a low cost test apparatus 200, a plurality of sockets 252 reside on the load board 246, for example, there may be four or eight sockets 252 on a load board 246, so that a set of IC""s may be tested with the low cost tests.
The low cost test apparatus 200 may be used to weed out devices that fail preliminary or pre-screening tests. The low cost test apparatus 200 and high cost test apparatus 100 may both be used to test IC""s for characterization tests, e.g., to ensure that specified electrical operational parameters are adhered to, and for production testing. The high cost test apparatus 100 and low cost test apparatus 200 are typically located at separate locations, a certain distance apart from one another, for example, on a production line.
Thus, in the prior art, a packaged integrated circuit typically is subjected to two separate test procedures in two separate test apparatuses, a low cost test apparatus 200 and a high cost test apparatus 100. Usually, a low cost test is performed on the packaged IC""s, and of the packaged IC""s that pass the low cost test, the good integrated circuits are then subjected to a high cost test which involves more stringent testing parameters at extreme temperatures, for example.
A problem with prior art integrated circuit testing is that packaged integrated circuits are loaded into the low cost test apparatus 200 and tested, and then the IC""s are unloaded from the low cost test apparatus 200, and subsequently loaded into high cost test apparatus 100. This introduces the chance that the packaged integrated circuits will be damaged, resulting in a loss or reduction in yield. Because the IC""s are loaded by hand by an operator, there is a likelihood of human error, and it is possible that bad IC""s will be mixed up with good IC""s, and vice versa. Furthermore, handling the packaged integrated circuits so often increases the chances that electrostatic discharge (ESD) will cause some of the integrated circuits to have failures, further reducing yields.
Another problem is that most high cost test apparatuses 100 are designed for single IC insertion: e.g., the load board 114 comprises only one socket 116. Thus, IC""s are being tested one at a time on the high cost test apparatus 100, which is inefficient, time-consuming, and costly.
What is needed in the art is a more efficient and economical IC test apparatus and method, as the prior art method of separating the tests is often foregone in favor of performing all of the IC testing on the high cost tester, which is a very expensive alternative.
What is also needed in the art is a test apparatus and method that avoids having to transfer integrated circuits from one test apparatus to another in order for the required tests to be performed on the integrated circuits.
Embodiments of the present invention achieve technical advantages as a test apparatus comprising a single handler coupled to at least a first tester and a second tester, when first test procedures from the first tester may be performed on a set of integrated circuits in parallel while second test procedures are being performed by the second tester on a different set of integrated circuits. The IC""s are loaded by an operator only once into the apparatus, and all of the required tests are performed on the IC""s while in the apparatus.
In one embodiment, disclosed is an apparatus for testing at least one first IC and at least one second IC. The apparatus comprises a first tester adapted to test at least one first IC with a first test procedure, and a second tester adapted to test the at least one first IC with a second test procedure simultaneously while the first tester tests the at least one second IC with the first test procedure. A single handler is coupled to the first and second testers, and the first and second test procedures are adapted to test at least some different IC parameters.
In another embodiment, disclosed is a method of testing at least one first IC and at least one second IC in an apparatus comprising a first tester and a second tester coupled to a single handler. The method comprises testing the first IC with a first test procedure using the first tester, and testing the second IC with the first test procedure simultaneously while testing the first IC""s with a second test procedure using the second tester. Testing IC""s with the first test procedure comprises testing at least some different IC parameters than testing IC""s with the second test procedure.
In another embodiment, disclosed is a method of testing integrated circuits IC""s, comprising providing at least one first IC, providing at least one second IC, testing the at least one first IC with a first test procedure, and testing the at least one first IC with a second test procedure simultaneously while testing the at least one second IC with the first test procedure. The first and second test procedures are performed within a single enclosed handler, and testing IC""s with the first test procedure comprises testing at least some different IC parameters than testing IC""s with the second test procedure.
Advantages of embodiments of the present invention include providing the ability to perform all required tests on integrated circuits with a single handler in a single test apparatus, improving integrated circuit yields and being more efficient than prior art IC test methods. Less handling of integrated circuits is required by operators, which decreases the chances for human error and decreases the chances that good IC""s will be mixed up with bad IC""s, and vice versa. More efficient use is made of the time on high cost testers, and there is less of a chance that integrated circuits will be destroyed or damaged by ESD.